FIELD OF THE INVENTION
The present invention relates in general to video synchronizing signal generators, and in particular to a circuit for deriving an offset video synchronizing signal from a video subcarrier.
In the European Television Phase Alternate Line (PAL) standard, a video frame has 625 lines, with 1125 pixels per line. A frame is formed by two interleaved fields of 312.5 lines per field. A video source produces a video signal conveying the color information for each pixel of a frame in succession on a line-by-line basis with the two fields for each frame appearing in succession. A display monitor, may for example, use the video signal to control the intensity of an electron beam as it sweeps across a cathode ray tube screen. One of the signals needed by the video source or display monitor is a horizontal synchronizing (sync) signal H indicating the start of each line of pixel information as it appears in the subcarrier signal.
A horizontal sync signal generator typically uses the video signal subcarrier signal frequency F.sub.sc as a reference to produce a suitable horizontal synchronizing signal H. In the PAL standard, the period (P.sub.H) of the horizontal synchronizing signal is related to the period F.sub.SC of the video subcarrier signal as follows: ##EQU1## Since P.sub.H is a large fractional multiple of P.sub.SC it is not practical to simply frequency multiply the SC signal by 2500 and then frequency divide it by 709379 to produce the horizontal sync signal H. Without the 25 Hz offset we could use a frequency multiplier to multiply the subcarrier signal SC by 4 and then use a simple divide-by-1135 counter to frequency divide the resulting 4F.sub.SC to produce the horizontal synchronizing signal H. However accounting for the 25 Hz offset requires more sophisticated circuitry.
Phase lock loop technology can produce an output signal having a period that is not an even multiple of the period of a reference signal. U.S. Pat. No. 4,268,853 issued May 19, 1981 to Nakamura et al, U.S. Pat. No. 4,328,513 issued May 4, 1982 to Furigato et al, U.S. Pat. No. 4,390,892 issued Jun. 28, 1984 to Banks, and U.S. Pat. No. 4,575,757 issued Mar. 11, 1986 to Aschwanden each describe circuits using phase lock loops to produce the PAL sync signal using the video subcarrier frequency as a reference. However phase lock loop circuits do not lend themselves to integration on a single IC.
Another approach to the problem is to use a signal other than the video subcarrier as a reference. U.S. Pat. No. 4,169,659 issued Oct. 2, 1979 to Marlowe describes a sync generator that uses an oscillator to produce a reference signal having a frequency that is an even multiple of the PAL sync signal. However a horizontal synchronizing signal that is not locked to the subcarrier signal can cause picture disturbances in some applications.
Yet another approach to the problem, as taught in U.S. Pat. No. 5,282,020 issued Jan. 25, 1994 to Tanaka, is to frequency multiply the SC signal by four and then use a counter to divide the result by 1135. The 25 Hz offset is ignored until the last line of each field when it is accounted for by dividing the frequency multiplied SC signal by 1137 instead of 1135. The extra two cycles of the multiplied SC signal accounts for the 25 Hz offset. Although this approach accounts for the 25 Hz offset, only the sync signal pulse of each frame matches the PAL standard, the timing of the other sync signal pulses for each frame varies from the PAL standard. This can distort the image somewhat and can be problematic in applications where timing is critical.
What is needed is a digital integrated circuit that can generate a PAL standard horizontal sync signal using the PAL standard subcarrier signal frequency as a reference without resorting to phase locked loop technology.